Consisting of four tools, the suite targets productivity in IC design using AI-powered automation to accelerate verification.
According to Abhi Kolpekwar, vice president and general manager, Digital Verification Technologies, Siemens EDA, the increased complexity of asic and FPGA design means that first-time silicon success rates is as low as 14% and 13% respectively. Faster simulators or engines are not sufficient to reduce the process and the workload to increase productivity, he continued, introducing the suite.
The suite supports large, complex designs from IP to SoC systems and was developed to scale up for advanced 3D-ICs, chiplet-based designs and software-defined architectures.
The first tool, Questa One, combines coverage with universal verification methodology constrained random test generation for coverage that is 50 times faster than traditional testbench solvers, said the company.
The design for test tool, DFT Simulation Acceleration software uses Parallel Simulation software to accelerate gate level DFT serial pattern simulations. This is integrated with the Tessent Streaming Scan Network (SSN) architecture.
The Questa One Fault Simulation Acceleration software has delivered 48x faster performance, reported Siemens, and supports both functional safety and DFT fault simulation applications. It also supports the User Defined Fault Modeling (UDFM) capability in Tessent.
To increase productivity, the Questa One Stimulus Free Verification software combines engines and unifying applications to reduce processing times from over 24 hours to under 1 minute on complex open source SoC level reference designs. It integrates 20 stimulus-free analyses, AI and automation to provide options such as linting with auto-correction and generative AI SVA property creation and verification.
Following the company’s acquisition of Avery, it has incorporated Questa One Avery Verification IP (VIP) software, based on its VIP and high-coverage compliance test suites (CTS). The same CTS, testbench and stimulus on Questa One Sim can be re-used on Veloce CS emulation and prototyping systems.
The Questa One tools will be available from June this year. Early adopters are reporting step-function gains across smart creation, smart regression, smart analysis, smart engine and smart debug domains, said the company.
Image: Siemens
See also: Siemens and IFS certify tools
