de Vries said that to integrate these non-CMOS technologies in a system-in-package (SiP) “requires an EDA environment we don’t have today”. “We are far from that,” he said.
However, both Cadence and Synopsys are confident they will be able to develop design tools to cope.
Mike Fister, Cadence chief executive, has tasked the firm’s chief technology officer Ted Vurcurevich and head of new business Aki Fujimura with investigating what is needed to build capable tools. In most respects the existing underlying technology should be suitable.
“If you look at what we as a company in an engineering sense know how to do, we know how to model things, analyse and optimise,” Vucurevich told Electronics Weekly.
“And so a lot of the recent trends in numerical modelling and analysis lend themselves to being applied in a very general way, to other problem sets.”
While there are abstracted languages that are more closely tied to a particular technology – SPICE with CMOS, for example – TCAD-type tools deal in physics and chemistry, and as such could be written to handle and use the behaviours of any system that functions according to these laws.
“As long as these things can be modelled by traditional maths – differential equations – [integrated SiPs] should be possible,” said Raul Camposano, chief technology officer at Synopsys.
Camposano added that if there are any elements for which a common modelling approach is not useful, biological parts in an SiP, for example, they could be accommodated as ‘black box’ units attached to a core system.
