Revealed at the Symposium on VLSI Technology and Circuits in Kyoto, it achieves data rates of up to 300 Gbit/s using PAM-4 modulation, said the Belgian research institute, which is aiming it at data centres.
“PAM-4 has emerged as the preferred modulation scheme in data centres, enabling faster data transfer without requiring more bandwidth,” it said.
5nm CMOS was chosen not for the best analogue performance, but because it is the preferred geometry for next-generation data centre ICs, said Imec, some of which will need comms links above 200Gbit/s/lane, and later 400Gbit lanes.
Power consumption in the technology demonstrator is 621mW from 900 or 960mV, partly due to picking an architecture with 34 rathe than 127 unit cells – Electronics Weekly has asked for more information.
“Looking ahead, the team aims to address the growing demand for even faster data links by targeting ADCs and DACs based on 3nm CMOS technology,” said Imec transceiver manager Peter Ossieur. “The focus is on doubling the sampling rate to 300Gsample/s and pushing bandwidth beyond 100GHz. To achieve such speed imec will draw on its expertise in analogue design and ultra-low-jitter clock generation circuitry targeting femtosecond-level accuracies.”
Earlier this month, Imec demonstrated high-speed optical links on silicon ICs
