Leakage at the 90nm process node was not as big a problem for Philips Semiconductors as it was for other chip companies because Philips scaled for cost rather than performance, said its CTO Theo Claasen.
“We can maintain the price erosion, but performance doesn’t scale, and power scales a little bit,” Claasen told Electronics Weekly at the 2004 MEDEA+ Forum.
“The leakage problem is an Intel problem, not a Philips problem, because Intel scales for performance. We don’t need performance. The applications don’t require it. So long as we can get the density improvement and the low-power, we’re satisfied.”
After the nightmare 0.13/0.12µm process node, scaling is back on track. “0.12µm was slower than expected because of yield problems,” said Claasen.
“90nm is extremely smooth. If you look at 65nm, it looks pretty promising – close to the timings we expected – there are no major problems. We’ll have 65nm in production at the end of next year.”
“The transistor design will be such that we reduce leakage,” added Claasen, “so we will first develop low-power versions to reduce leakage – I think we will be successful there. We shouldn’t under-estimate the influence of design – Philips has come up with current solutions which deal with all the problems.”
In 2008, three years after the introduction of the 65nm process, Philips expects to have 45nm in production.
Philips Semiconductors is bringing up processes to the same time-scale as the foundry, TSMC. So why does Philips bother investing in CMOS manufacturing? “To be master of our own destiny,” replied Claasen. “The cycle means you have to recover money in the up-cycle. You can make money if you have available the capacity to do that.”
